History is littered with the ruins of failed memory technologies. But former Intel CEO Pat Gelsinger believes an emerging memory tech developed by researchers at Georgia Tech using oxide semiconductors may be the exception to the rule. "Essentially, we’ve had no major forms of innovation in memory for three decades – SRAM, DRAM, and Flash as the only memory types in broad deployment," Gelsinger told El Reg . Nagare Labs’ Z2RAM aims to change that by delivering a memory tech that’s nearly as fast as SRAM at a density much closer to that of DRAM, while also being easier to manufacture than HBM or LPDDR. "Fundamentally, they are combining the best characteristics of DRAM, SRAM, and flash into a new device that is both dense like DRAM, fast like SRAM, and scalable like flash," Gelsinger said. "While HBM has many limitations (power, density, shoreline bandwidth) the combination of its density and performance is the best available today. This is exactly the value that Z2RAM brings, giving better density, speed and power." This explains why investor Playground Global, where Gelsinger became a partner last year, is helping to bankroll Nagare’s development efforts. SRAM-like speed, DRAM-like density
Founded by Georgia Institute of Technology professors and researchers Suman Datta and Shimeng Yu, Nagare Labs is the culmination of years of research into next-generation memory technologies like ferroelectrics and resistive RAM. The technology is being built on oxide semiconductors and is designed to be integrated directly onto compute logic using 3D hybrid bonding technologies. In this respect, Z2RAM will fill a similar role to AMD’s 3D V-Cache SRAM stacking tech. If you’re familiar with CPUs requiring additional L3 cache, AMD uses advanced packaging to bond a 64MB SRAM tile either above or below its CPU chiplets, effectively tripling their SRAM capacity. Z2RAM is similar in concept, but promises bit density upwards of 5x that of SRAM in its first incarnation. So if you were to look at a 64MB SRAM tile, Nagare’s Z2RAM tiles would offer 320 MB of capacity in the same space, at bandwidth comparable to SRAM. While that may not sound like a lot of capacity compared to HBM-heavy accelerators like Nvidia’s Rubin with its 288 GB capacity, or AMD’s MI455X with its 432 GB, Z2RAM presents a major improvement over SRAM-based accelerators like Nvidia’s Groq LPUs. Today, Nvidia’s Groq 3 LPUs feature about 500 MB of SRAM per chip, necessitating thousands of accelerators in order to serve frontier LLMs at scale. Z2RAM could cut the number of chips required by 5x or more. "With the explosion of AI demand, we’ve seen an extraordinary demand in memory as AI is a memory-limited workload. With that backdrop, there is extraordinary interest and now capital available for a breakthrough that solves the bandwidth and capacity challenges that AI is creating," Gelsinger told us. Look Ma, no capacitors
Nagare achieves this density and bandwidth feat using memory cells based on transistors rather than capacitors…