AMD’s Epyc X-chips are back after a three-year hiatus

AMD’s cache-packed Epyc X chips are officially making a comeback. Based on the House of Zen’s frequency-optimized SKUs we looked at back in September , its HPC-optimized Venice-X parts will offer up to 96 cores and use the company’s 3D V-Cache chip stack tech to triple the L3 cache density to more than a gigabyte. But before you get too excited about another cache-packed Epyc, it’ll be a little while before they actually ship. AMD expects the Venice-X to begin trickling out in the second half of 2027. First teased at CES earlier this year, the chips are primarily aimed at latency-sensitive technical and scientific computing workloads like computational fluid dynamics and electronic design automation (EDA). AMD itself relies heavily on its X-series Epycs for EDA workloads like functional verification testing, which is used to simulate silicon in order to ensure it behaves as it’s intended to. According to AMD Fellow Phil Steinke, by keeping more of the model in cache, the CPU cores don’t have to wait as long for data to move in and out of system memory. Normally, boosting L3 capacity would have required larger chiplets with lower yields, but that’s not how AMD has gone about it for the past four years. Instead, it used advanced packaging to give its existing CPU dies a little SRAM backpack. This tech has been around for several generations now, having first debuted in the Ryzen 7 5800X3D back in 2022. That consumer desktop chip stacked a 64 MB SRAM tile on top of an 8-core chiplet, boosting L3 capacity to 96 MB. The extra cache made the chip one of the most potent gaming CPUs of the time. Later that year, AMD brought the same technology to its Milan generation of Epycs as the company expanded its portfolio to address a wider range of workloads. The extra cache was popular enough to justify a second generation of X-series Epycs, which launched in 2023. But then, nothing. When AMD unveiled its 5th-gen Epycs in late 2024, there was no Turin-X on the roadmap. According to Madhu Rangarajan, who runs AMD’s compute and enterprise AI products biz, this was intentional. "We are not doing the X every generation…. The enterprise HPC kind of market tends to have a cadence that’s a little bit slower, so that’s what drives our cadence."…